In this project, you are required to write a trace cache simulator. The processor is assumed to be order processor. The Cache has a size, line size, and associativity that are powers of 2. The cachedirect-mapped, set-associative, or fully-associative.
The input to the simulator is a trace of data accesses (all loads) generated by the processor. The ile is a binary file (not a text file) and includes 1 million data accesses. Each access is made up obyte unsigned integer byte address. Therefore, the size of each trace file is: 1,000,000 x 4 = 4,00Bytes.
When your program is run, it must ask the user to enter all the following:
• The name of the trace file.
• The number of accesses to simulate.
• The cache size in bytes (a power of 2).
• The block size in bytes (a power of 2).
• The associativity (a power of 2). An associativity of 0 indicates a FA cache.
• The cache replacement policy: ‘L’ for LRU and ‘O’ for OPT.
After completing the simulation, the program should print out the number of hits and misses
experienced by the cache.
programming in C ...