VHDL code of pulse width modulation PWM


(system) #1

[LEFT]i’m writing a code of a 4 bit pulse width modulator with the following code

[SIZE=4]llibrary ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity PWM is
port(CLK : in std_logic;
D : in std_logic_vector (3 downto 0);
PWM : out std_logic);
end PWM;
architecture Behavioral of PWM is
signal tmp : std_logic_vector(3 downto 0);
signal up_down : std_logic;
signal Oup : std_logic;
signal TC : std_logic;
begin
process (CLK, TC, tmp)
begin
if (CLK’event and CLK = ‘1’ and TC = ‘0’) then
if (up_down = ‘1’) then
tmp <= tmp + 1;
elsif (up_down = ‘0’) then
tmp <= tmp - 1;
end if;
elsif (TC’event and TC = ‘1’) then
tmp <= D;
Oup <= not Oup;
PWM <= Oup;
up_down <= Oup;
elsif (tmp’event and tmp = “1111”) then
TC <= ‘1’;
elsif (tmp’event and tmp = “0000”) then
TC <= ‘1’;
end if;
end process;
end Behavioral;

but i keep getting the following error when viewing the RTL schematic[/size]

ERROR:Xst:2358 - “C:/Users/Mazen/Documents/VHDL Projects/First/PWM/PWM.vhd” line 45: Operands of <AND> are not of the same size.


any ideas ?? [/left]


(system) #2

goooooooooood atempt